This section endeavors to supply a context or background for the various exemplary embodiments of the invention as recited in the claims. The content herein may comprise subject matter that could be utilized, but not necessarily matter that has been previously utilized, described or considered. Unless indicated otherwise, the content described herein is not considered prior art, and should not be considered as admitted prior art by inclusion in this section.
Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field effect transistors (FETs) and capacitors, for example. Circuit chips with hundreds of millions of such devices are not uncommon.
Basically, a FET is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate. As known to those skilled in the art, P-type FETs (pFETs) turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current. On the other hand, N-type FETs (nFETs) turn ON to allow current flow from source to drain when the gate terminal is high or positive with respect to the source. When the gate potential is negative or the same as the source, the N-type FET is OFF, and does not conduct current. Note that in each of these cases there is a threshold voltage (e.g., at the gate terminal) for triggering actuation of the FET. More than one gate (multi-gate FETs) can be used to more effectively control the channel.
As transistors have become smaller in size and the currents they convey become commensurately smaller, it has become more important to control for current leakage by disposing the gate on more than simply the top surface of the channel, as was done with early transistors. As such, more effective gate control can be obtained by disposing the gate fully about the cross-sectional profile of the channel to form a gate-all-around (GAA) transistor.
Nanotechnology has gained widespread use in the semiconductor industry as a way to meet scaled technology requirements. One-dimensional nanostructures such as silicon nanowires (SNW) are attractive building blocks for assembly of nanoelectronic and nanophotonic systems. Nanowires are particularly attractive because their electronic and optical properties can be tailored by controlling their diameter through synthesis.
Semiconductor nanowires have been utilized to construct various devices including, for example, FETs, complementary metal-oxide semiconductor (CMOS) FETs, logic gates, sensors, photodiodes and lasers. In particular, semiconducting nanostructures (e.g., nanowires and nanocrystals) can be used as the “channel” material in a FET. One common method of fabricating a nanostructure FET deposits the nanostructure on a substrate (e.g., an oxide thin film) from a liquid suspension. Source and drain contacts are then formed lithographically on the nanostructure.
Nanowires can be formed from semiconductor materials including, for example, Si, SiGe, a III-V compound semiconductor, or a carbon nanotube (CNT) for use in the active channel area. Such nano-channels may be patterned with a conventional “top down” lithographic patterning technique or from a “bottom up” process with nanowire or CNT deposition atop a semiconductor substrate (e.g., Si, SiGe, a Silicon-on-insulator, a semiconductor-on-insulator (SOI) or a silicon germanium-on-insulator (SGOI)) followed by conventional gate patterning such as those outlined in U.S. Patent Application Publication No. 2008/0305437 and U.S. Patent Application Publication No. 2008/0045011 or other methodologies.
FIG. 1 shows a cross-section of an exemplary GAA Schottky junction source/drain FET 110 having a channel using a nanowire 112. The FET 110 is embodied within a semiconductor structure 100 that comprises the FET 110 disposed over a buried oxide layer (BOX) 102. The FET 110 has a nanowire (NW) 112 connected to a silicided source region 114 and a silicided drain region 116. The FET 110 further includes a gate structure 120 that surrounds the NW 112 (e.g., at least a portion thereof). The gate structure 120 may comprise a gate stack 122 having one or more layers that comprise one or more dielectric materials, one or more metals and/or one or more insulating layers (e.g., an oxide). In some cases, the NW 112 is enveloped (within the gate structure 120) by an interstitial layer of gate oxide 124 to enhance electrical coupling of the gate stack 122 to the channel (the NW 112). The gate structure 120 further includes a cap 126 (e.g., a silicided cap) and one or more spacers 128. The BOX 102 may overly one or more further layers, such as a semiconductor layer (not shown). As an example, the FET 110 may be formed over a SOI substrate with the top semiconductor layer being used to form the source 114 region, drain 116 region and/or channel (NW 112) of the FET 110.
The GAA structure has potential for improving performance of extremely-scaled FETs. In addition, Schottky junction source/drain technology may enable reduction of the parasitic source/drain resistance.